1. Field of the Invention
The present invention relates to receivers and more particularly to differential receivers for use in information processing systems.
2. Description of the Related Art
In computer and information processing systems, various integrated circuit chips must communicate digitally with each other over common buses. The receiving bus nodes recognize the signal as being high or low using receivers, which are also referred to as input buffers. Often the receiver is a differential receiver, i.e. a receiver that detects the difference between two input signals, referred to as the differential inputs. These input signals may be a received signal and a reference voltage or they may be a received signal and the inverse of the received signal. In either case, it is the difference between the two input signals that the receiver detects in order to determine the state of the received signal.
Integrated circuits are powered at certain voltage levels, which levels are then provided to the various components, such as the receivers, which are located on the integrated circuit. However, the nominal supply voltage for integrated circuits keeps being decreased to reduce power consumption. Additionally, fluctuations of the voltage level during operation can make the voltage level powering a receiver even lower. The lower the supply voltage, the more challenging it is to get a receiver to operate reliably.
The signal frequency at which communication occurs can limit the performance of the overall system. Thus the higher the communication frequency, the better. The maximum frequency at which a system communicates is a function not only of the time that it takes for the electromagnetic wavefronts to propagate on the bus from one chip to another, but also of the time required for the signals to be reliably recognized at the receiving bus nodes as being high or low. Characteristics which affect the time in which a signal is recognized by a receiver include the set up time of the receiver, i.e., the amount of time before a clock edge that a signal must arrive and settle to a recognized level, and the hold time of the receiver, i.e., the time after a clock edge that the received signal must stay at a certain level in order for that level to be detected by the receiver. Other characteristics that affect the ability of the receiver to determine that state of the received signal include the ability of the receiver to reject input noise and power supply noise and the ability of the receiver to resolve small voltage differences between the differential inputs of the receiver.
It is desirable to provide a receiver which can receive signals provided by drivers of different types. Examples of types of drivers include High Speed Transmission Logic (HSTL) drivers, Dynamic Termination Logic (DTL) drivers, and Pseudo Emitter Coupled Logic (PECL) drivers.
It has been discovered that a receiver may be provided which quickly and efficiently recognizes signals by providing the receiver with a resolving circuit which is coupled to a differential current source which converts the signals to currents that produce differential voltages on first and second nodes, the difference in voltage being resolved by the resolving circuit. The differential source is in shunt (not in series) with the resolving circuit. The timing with which the differential source interacts with the resolving circuit is such that the signal to noise ratio is maximized.
Such a receiver advantageously operates with low power supply voltage levels, allows a small sampling window, i.e., a small sum of setup time requirement and hold time requirement, and quickly resolves a differential. Other advantages of the invention include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 millivolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL or any other driver type which uses a differential signal.
More specifically, in a preferred embodiment, the invention relates to a method for determining the value of a differential input value. The method includes: generating a first current based upon a first part of the differential input value, the first current generating a voltage at a first node; generating a second current based upon a second part of the differential input value, the second current generating a voltage at a second node; resolving which of the first and second nodes has a higher voltage based upon which of the first and second currents is higher reinforcing which of the first and second nodes has a higher voltage during the resolving step by amplifying a differential voltage imposed by the first and second currents at the first and second nodes, so as to enhance the resolving step; beginning reinforcing after the differential voltage is imposed by the first and second currents.
Additionally, in another preferred embodiment, the invention relates to a method for determining the value of a differential input value. The method includes the steps of providing a resolving circuit coupled to a clock signal, the resolving circuit having a first threshold voltage at a first and a second node below which a first portion of the resolving circuit turns on and a second threshold voltage at the first and second node above which a second portion of the resolving circuit turns on; coupling a first part of the differential input value to a first node; coupling a second part of the differential input value to a second node; using the clock signal to power the resolving circuit so as to allowing determining the value of the differential input value when the first or second node voltage exceeds the second threshold voltage of the resolving circuit; using the clock signal to turn on the second portion of the resolving circuit after the first portion of the resolving circuit is turned on.